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Dedicated Chip Design for the Generation of colors through RGB LEDs

Masterarbeit 2011 69 Seiten

Informatik - Technische Informatik

Leseprobe

ABSTRACT

Aim of this research work is to design a Red Green and Blue (RGB) Light Emitting Diode (LED) pixel driver that makes the development of RGB displays easier especially for small to medium size display boards. The existing system is using conventional shift registers fed by a local Field Programmable Gated Array (FPGA) based driver. Our intent was to have a single chip which can receive serial data and contains a surrogate controller to generate the different intensities by driving the RGB LEDs which might produce different colors.

In our research, the core architecture of the controller chip is an eight bit (per color) wide Pulse Width Modulation (PWM) controller which generates 16.7 Million colors. Total PWM width for the three basic colors is 24 bits wide (per pixel). The chip contains 48 parallel PWM outputs along with serial-in-serial out data pins and other control inputs.

After the successful simulation at behavioral level and post synthesis simulation; the design is transferred to schematics and then to layout. Mentor Graphics tools set for Application Specific Integrated Circuit (ASIC) Design flow are used with ASIC Design Kit from MOSIS having technology and feature size of AMI-0.5um or TSMC-0.35um. The dedicated design and its subsequent analysis have ramifications for chip-design engineers working in optoelectronics or photonics engineering industry.

ACKNOWLEDGEMENTS

I would first of all pay my thanks to Almighty Allah for His providential guidance, analytical wisdom and vigour to put my best possible effort towards the accomplishment of this thesis.

I express my gratitude to my venerable supervisor Prof. Dr. Ahmed Shuja Syed, Dean FET, IIUI for his vital support and constant encouragement towards the completion of this thesis. I also express my gratitude to him, he being the Dean and Chairman, FET provide his unforgettable support during my work.

I also express my gratitude to all of my teachers for their kind contribution in my knowledge and expertise. I am also indebted to the project director IC Design Center Lab, Mr. Shahid Ahmed Khan for his unconditional support throughout my research work.

I am also thankful to all members of MS/PhD Committee for their kind guidance to ensure the quality of work in my dissertation.

Chapter No 1 Introduction, Background and Literature Survey

In this chapter, some general topics of this MS thesis will be introduced such as the goal of this research, the major challenges of this project, methodology of our study and the structure of this report.

1.1 About the thesis

This MS thesis is a special topic under the VLSI system design which involves the Micro-electronics and Digital Design techniques required for the professionally developed LED based electronic displays.

The goal of this thesis is to design a dedicated chip to produce true colors on RGB LEDs based on the previous implementation of the design with FPGA. We aim to start with an abstract description of the outdoor LED display architecture with different organization-level structures on a hardware/software design strategy, and find an optimum solution for cost effective design which in turn can be easily/efficiently implemented while reducing the software and hardware overheads.

1.2 The Design Procedure

The design procedure or the operational methodology is generally planed in the following phases:

i) Core design of the hardware based on the optimized architecture/organization.
ii) HDL coding in modular form.
iii) Behavioral simulation and verification by comparing the results with required timing.
iv) ASIC technology dependent Synthesizing the technology independent Netlist.
v) Post synthesis simulation of the technology dependent netlist to verify the synthesis process.
vi) Schematic generation from the technology Netlist.
vii) Layout design and its verification with caliber.

viii) Post Layout Simulation.

Most important phase of the project is the HDL coding which should be optimized and retained modular. If coding style is not optimized, it will lead to a larger circuit and thus the chip area will be increased. To keep the design manageable both in schematic level as well as layout level, the design must be modular at functional level. From a device design engineer’s point of view, it is at times impossible to work with a large single layout block, and therefore alternative strategies are required to embed in the system level product design.

1.3 The Major Challenge

Among various complex issues to be resolved during the design processing of this study, the major challenge of this project is to design a core module of the surrogate controller which will receive serial data and generate the intensity voltage “locally” in real time environment. It is important to realize that by “Real time” we mean the frame time of the operational electronics linked with the design processing- the time for which one frame will stay at the LED panel.

1.4 Report overview

This report is composed of the following five chapters:

Chapter 1: We will talk about some general background of electronic displays including single color multi color and true color RGB Display and need of improving the existing solution

Chapter 2: The chapter describes software research, HDL Design and Concept of the proposed Design.

Chapter 3: In this chapter, we will present the experimental conditions and results, and discuss them in detail with reference to the Behavioral simulation (with ModelSim), Synthesis (with Leonardo Spectrum) and Post Synthesis simulation (with ModelSim).

Chapter 4: This chapter contains the discussion on the results with reference to the Schematics and Layout design of PWM Controller

Chapter 5: A final conclusion on this study together with a brief description of further work is presented in this chapter.

1.5 RGB Color

The name RGB comes from the initials of the three primary colors, Red, Green, and Blue. RGB colors are additive in which Red, Green, and Blue light beams are added together to produce other colors. Each light beam is a wavelength when the three wavelengths are added (by emitting from a Introduction, Background and Literature Survey dark surface) as a result their spectra is added to make the final color on the color spectrum. Each of the three wavelength is called a component of that color, and each of them can have an arbitrary intensity from fully off to fully on. Color can be changed by changing the intensity of any component or two or three at a time. RGB is a device- dependent color model different devices (like CRT, LCD, LED) reproduce a given RGB value differently.

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Figure 1.1, The RGB Gamut

Three primary colors (Red, Green and Blue) are not sufficient to reproduce all colors;

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Figure 1.2

Normalized Response of human cone cells to Short, Medium and Long wavelengths (Red, Green, Blue) wavelengths respectively.

only colors within the color triangle defined by the chromaticity of the primaries can be reproduced by additive mixing those colors of components[26].

The choice of primary colors is related to the physiology of the human eye[26]. Its response to the wavelengths labeled Long, Medium and Short (Red, Green and Blue respectively) is shown in the figure-1.2[26]. Good primaries are stimuli that maximize the difference between the responses of the cone cells of the human retina to light of different wavelengths, and that thereby make a large color triangle shown in the figure 1.1.

1.6 Representation of (RGB)

A RGB triplet (r, g, b) represents the three-dimensional coordinate of the point of the given color within the cube or its faces or along its edges expressed as quantized samples of the possible values using only integer numbers within some range (0-255 for

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Figure 1.3

8-bit integer representation offers 256 distinct values of a component

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8-bit). If all the components are at zero the result is black if all are at maximum the result is the brightest representable white.

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Figures 1.1, 1.2 and 1.3 are obtained from Wikipedia (an internet resource).

1.7 Truecolor

True-color defines 256 (0-255) shades of Red, Green, and Blue for each pixel of the digital picture, which results in or 16,777,216 (approximately 16.7 million) color variations for each pixel. Truecolor RGB display mode does not need a color look-up table.

1.8 RGB LED Display

RGB color model is used to display colors on CRT, LCD, Plasma, or LED display such as a television, a computer’s monitor, or a Large Scale LED Screen. In case of LED Display each pixel of the screen is a RGB light source made from 4 LEDs (2-Red, 1-Green 1-Blue). LEDs of the Pixel are placed very close but still separated RGB light sources and so as the pixels.

Distance between LEDs of a pixel and LEDs of adjacent pixels is equal. At common viewing distance the separate sources are indistinguishable, which tricks the eye to see a given solid color. All the pixels together arranged in the rectangular screen surface conforms the color image. Commonly used RGB pixel is shown in the figure 1.4.

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Figure 1.4

4 RGB Pixels. Each combination is (RRGB)

There is no restriction on the shape of LED for RGB LED screen but size of the pixel is important to decide about the minimum viewing distance. For Large Scale LED displays LEDs with wide viewing angle are used as shown in the above figure. Its horizontal viewing angle is grater then the vertical one.

There is a bar shown over each pixel, it is a small projection of plastic or fiber slightly longer then the LED projection from the board, to stop the sunlight directly falling on the LED. Direct Sunlight falling on the LED degrades the color quality by adding other wavelengths. It also reduces the brightness of the pixel and may introduce flicker if the screen refresh rate is below or near the Critical Flicker Fusion Frequency (CFF). The flicker fusion threshold is proportional to the amount of modulation if brightness is constant, a short flicker will express a much lower threshold frequency than a long flicker. The threshold also varies with brightness of the source (it is lower for a brighter light source) and with location on the retina where the perceived image falls. CFF is directly proportional to ambient light level and is given by:

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1.9 LED Display Organization

LED display is basically a two dimensional array of LED pixels. An array of white LEDs is shown in the figure 1.5. Designed at TechServe (Peshawar).

Horizontal pixels are connected in a row by connecting their anode to common supply voltage. And the cathodes are connected to a constant current controller which sinks the LED current if the corresponding bit is high otherwise the sink path is

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Figure 1.5

Red Color LED Display 120 X 24 pixels array

open. Current controller is feed through a serial in parallel out shift register the shift register should also have a serial out port for cascading. Number of serial register and current controller depends upon the number of pixels connected in series. In a single color display one bit of a register and one current buffer is required for a pixel (single LED or the group of LEDs if connected in series within a pixel). A controller is required to fill the serial shift registers with appropriate data in the required time. The driving controller is responsible to take care of timing like frame time display refresh time and display blank time.

Row Multiplexed Model:

Display panel and interconnect structure is shown in the figure 1.6. A set of serial-in- serial-out-parallel-out shift register and constant current driver, commonly called the Drive Circuitry is mounted on the backside of each panel PCB.The row driver circuitry is connected at the end of a row in small size boards containing high power MOSFETs whereas in large display boards the row driver circuitry is part of the column (pixel) driver PCB mounted behind the LED panel PCB or a group of panel PCBs containing medium power MOSFETs.

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Figure 1.6

The row-multiplexed model is a low component count model normally used for low color resolution and low frame rate. Additionally high power MOSFET with very low drain to source voltage (VDS) are required for row selection, which make the design more complicated, and required heat sinks. Number of pixels per row depends upon the power of MOSFET. Row selection method also introduces a lot of flicker because all the multiplexed rows are scanned and only one is on at a time. Operating between the two consecutive rows the previous must be switched off before the second is switched on. This is necessary so that the human eye can clearly distinguish, without the off-time or if of-time I too short an overlapping occur among the multiplexed rows of a group. The scanning should be completed in frame time including off-time if not the frame rate will be dropped. Blanking a row is sufficiently fast due to the Gated PWM. When the Gated Enable Signal is disabled by the main controller and the corresponding row is switched off. Even if the scanning speed is fast enough the overall intensity is lower because the pixel on-time of a row is divided by the number of multiplexed rows.

The row multiplexed scheme was implemented with 27 colors on an indoor RGB Dot-Matrix display shown in the figure 1.7. This board was designed in the Large Scale Electronic Display Project (LSEDP) approved from the Federal Ministry of Science and Technology. This project of LSEDP was proposed and executed by National Institute of Electronics (NIE) (2003-2005). The board is capable of displaying picture in 27 colors. The picture is formed on four modules each of size one square feet and each module contains its own row driving circuitry with 40 pixels in a row.

Non Multiplexed Model:

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Figure 1.7 27 Color RGB Picture. Obtained from NIE.

For a non-multiplexed display panel each row of pixels is considered separately not like the row multiplexed model, here separate set of shift registers and constant current drivers are used for each row. This configuration is used for high color resolution and high frame rate displays. Component count of non multiplexed organization is higher than the multiplexed model. It is not necessary for a display to be a full color and can display movie

1.10 RGB LED Panel

RGB LED panel of 16mm pitch is shown in figure 1.8. The panel is designed for outdoor LED display with direct sunlight protection and non multiplexed rows. PCB of the driver circuitry for the LED panel is shown in the figure1.9. This PCB was designed during the LSED project at National Institute of Electronics (March 2007). Circuit shown in figure 1.9 is mounted in parallel behind the LED panel through the header

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Figure 1.8

Picture of a commercial RGB Panel

connectors which are mentioned in the figure 1.9. The driver chip used is (TB62726) which is a Serial-In-Serial-Out-Parallel-In-Parallel-Out shift register and Constant Current driver with a single resistor current adjust. Connectors for Serial Data In Serial Data Out along with control signals are shown at the left and right side of the PCB.

On each PCB there is a signal repeater normally the HCT series (High Speed CMOS TTL Compatible) buffer are used to restore the signal voltage. Which may fall down below the minimum noise margin while traveling through serially connected PCBs. All the signals need to be reshaped except the three data signals (Red Green and Blue) because they are reshaped each time when transferred from one IC to the next connected serially on a PCB. In this case there are eight shift registers (out of 32) connected in serial for single color on each PCB therefore the data signal is reshaped eight time when it pass through a PCB. But in all the existing circuits the color signals are also passed through the buffers.

Back view of Shift Register based LED Panel

1.11 Video Wall Structure

The above mentioned PCB is used to drive 128 RRGB pixels (16 × 8). This driver PCB, LED panel along with LED housing and sunshades is called LED Brick. The LD Brick size for 16mm pitch is (10 × 5) Inch. Size of LED Brick depends upon the distance between the LEDs constituting the pixels. The organization of 16 horizontal and 8 vertical pixels is common. LED video walls are normally made from Cabinets placed horizontally and vertically. Cabinet size is approximately one square meter which contains 24 LED Bricks. Each cabinet has its own FPGA based controller which received data in composite video format from a common cable connected to all cabinets of the video wall. The shift registers has nothing with the generation of colors on LEDs they just receive data streams generated from by the FPGA based controller which contain ON/OFF information of LEDs. The controller is sending data packets to shift registers in very high speed such that movies are displayed without flicker. A data requirement of one frame (Image) of data in 16.7 M colors (8-bit colors) for a board size of one cabinet (24 LED Bricks) is given as:

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Table 1.1. Data Requirement of a single cabinet for one second (30 fps, 8-bit colors).

Approximately 11.25 MB of data is required for 1 second of movie @ 30 frames per second. If frame rate is higher than 30 (50 fps is normal in LED displays) the amount of data will be increased.

Data Rate Requirements

Data rate required for one row is taken to estimate the minimum bandwidth because the controller is feeding them in parallel. Shift registers for different rows are not connected separately but a group of serially connected shift-registers is dedicated for a single color. Even the two red colors within a pixel are in separate groups. The inter-connect structure is an interleaved one to minimize the PCB design. There are 32 shift-registers on each LED Brick (8 for Red1, 8 for Red2, 8 for green and 8 for blue). Only 4 shift-registers are connected in series. Data of each color is transferred through an independent channel of shift-registers. This will reduce the bandwidth requirements of serial channels but increase the number of parallel outputs to feed the shift registers.

For one LED Brick there required 8 simultaneous serial out puts. Minimum data rate required for 64 horizontal pixels of a one Sq M cabinet is given in table 1.2.

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Table 1.2. Data Rate for one cabinet for one second (30fps, 16.7M colors). Page | 9

The 240KB data rate is not a big deal. This calculation is just for understanding actual data rate should be greater than 240K because there are control signals like clock and strobe for which the data must follow setup and hold time requirements. This data rate will be increased @ 240 KB for a single cabinet connected horizontally and frame rate of 30 is not common for LED displays. Professional available displays offer frame rate of slightly greater than 50 fps.

Brightness Control

Brightness / Hue control can be achieved by Pulse Density Modulation (PDM) which can be defined here as the occurrence of Pulse Width Modulation (PWM) in the time allotted for one frame of data. In the following figure one frame which contains multiple sub-frames is shown. Number of sub-frames depends upon the highest clock speed supported by the design. Addition of this feature (Brightness Control) will increase the bandwidth requirements of the system. If 30 intensity levels are added to the example above the required data transfer rate will be (240 KB ×30= 7200KB) which is the theoretical calculation actual will (10-15) % higher.

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Figure 1.10 Timing Diagram for the proposed PDM scheme

All of the above calculations are only for a length of 40 inches (i.e. 4 horizontal LED Bricks). If board size is increased everything will be changed. So there is a need to have a system which does not require a large and faster FPGA based controller and high data transfer rate from the main controller to the LED Driver ICs. Therefore, a surrogate controller is proposed which will be mounted on the LED Brick. This controller will be responsible to create the colors through PWD and control Brightness with PDM.

1.12 Literature Review

This part of the thesis is totally dedicated to the concerned literature studied during the design process of the chip. This has formed the bases to review our work in line with the available data techniques and process to efficiently and effectively design the generation of colors through RGB LEDs.

Techniques suggested by Svilainis[1] allow the significant increase in gray level and the image refresh frequency for serial driven large scale LED displays. Need of large number of grayscale levels and high refresh rate is also explained. It is also concluded that the Implementation of Binary Weighted PWM with similar amount of over head reduces the electromagnetic interference[1].

Svilainis performed an important experiment where they used the basic knowledge of LEDs with the advance level of synthesis techniques. LED forward current is non-linear therefore, LED dimming is implemented with Pulse Width Modulation. A constant current driver is also required with PWM for a linear light control of LED[1]. It is interesting to note that the human sense of light is non linear therefore higher levels of intensity codes are required to drive LED. Some codes have to be removed to create the desired control law. Single current driver have to be used for a single LED. Data is transmitted serially which reduces the number of transmission lines[1]. The LED display image refresh frequency has to be limited to certain level thus restricting the number of attainable LED intensity levels. These mentioned limitations are overcome in this study[1].

The Gated PWM (GPWM) LED dimming technique suggested for LED video displays. This study needs the large number of grayscale levels. The technique is applicable when serial transmission of LED driver’s data is used[1]. It offers a significant increase of gray levels compared to PWM and BPWM. There is an insignificant decrease in the total light output[1].

For the worst case analyzed the reduction in maximum achievable intensity is about 5% if 256 LED are driven serially and 1 kHz refresh frequency is used[1]. GPWM maintains the advantages of the binary PWM: the controlling data flow and the amount of buffer memory used for the processing and storage is low. The switching pulses are spread in time so produce less EMI than the linear PWM, which is the main highlight of this study[1].

Design process of the ASIC’s used for geometry and rasterizing graphics is traditionally started from schematic design as functional blocks and then transferred to netlists[2]. It may be fine at top most hierarchical level but difficult and error pron at the gate levels. These custom ASICs are targeted through silicon compilers. This is very expensive especially for university laboratories with high non-recurring engineering coats (NRE)[2]. The study done by White er.al.[2] presents an alternative approach i-e the top down ASIC design with logic synthesis and further optimized for the targeting FPGA / ASIC. In addition, FPGA, FPIC, and MCM technologies are available at a fraction of the cost of ASIC.

Top down ASIC design approach is the fastest and easiest way to complete a design process with verification after each stage[2]. The HDL based process reduces the non-recurring engineering cost and it requires a strong logic construct, otherwise false signals may be added to the design [2].

Study conducted by Collis[3] is specific to encourage designers to use Top Down design approach using HDLs. It also explained the steps and important things to remember during the process. This study is to address the complexity of digital system which is growing rapidly and it imposes pressure on designers to complete design in minimum possible time. Therefore the designers are forced to use top down design hierarchy using HDLs and automatic synthesis tools for the translation of design to gate level representation[3].

HDL based design process is examined and some requirements regarding the tools used during the process are observed by Collis[3]. It involves the integration of tools, and some important findings are as follows[3].

I. Standard Dataflow Diagram and Finite State Machine needs to be specified in the VHDL Verilog HDL base design so that it can easily communicate between the different tools used in the design process and also to partition the design.

II. Simulation and Synthesis needs to be done with a common HDL based tool. So that risk of different interpretation of different tools is eliminated.

III. Post synthesis simulation is desired where to performance gate level simulation.

IV. The optimization tool should insert scan chains and booth the optimizer ATPG needs to be integrated closely.

This level of integration is only provided by the Mentor Graphics ASIC Design Tools in this study.

For the VLSI design system process selection is important to successfully complete the design according to specification[4]. Tools selection is also important for the efficient and in time completion, which keep the design cost low[4].

An adaptive FIR filter is implemented through Mentor Graphics Tools[4]. Original design of the ASIC was produced in MATLAB and then translated to VHDL which is then synthesized to TSMC 0.25um process. The design is composed of 17,654 transistors and core cell area of 0.562milimeter square[4]. MATLAB and Mentor Graphics ASIC Design tools are used for the implementation of adaptive FIR filter, which is synthesized to TSMC 0.25um process[4].

Gate level design of schematics is obsessed due to the Hardware Description Languages, which are further, translated to device level by sophisticated synthesis tools[5]. This advancement changed how to create the digital electronics. To utilize the power of HDL tools the designers have to understand the complete flow of this process along with hardware of the design[5]. The paper by Raymond et. al.[5] reviews the experience obtained on using hardware design methodologies on Mentor Graphics tools.

Design and fabrication of VLSI chip requires many methodologies. Currently the four methodologies are used[6] i-e silicon compilation, standard cells, synthesis and full custom, each of them have its own pros and cons[6]. The full custom methodology is investigated (for which the design is prepared at transistor level) by Schneider et al[6].

The Mentor graphics EDA tool is selected for the creation of the design, which is reliable, efficient and fully integrated. A designer may start from the device level schematic entry to the final fabrication drawing including simulation and verification after each stage[6]. Most of the educational and research institutions are using commercial CAD tools for the VLSI design methodology. The full custom VLSI design methodology is selected because it requires in depth understanding of the design and its transistor level characterization in this study[6]. Mentor Graphics design environment is more useful in the way that it provides the commercial design tool in the educational domain, they differ only in the licenses not in the environment. Full custom VLSI design methodology is discussed with an 8-bit ALU circuit in this study[6].

A comparable study is also available in the datasheets provided by the MAXIM Integrated Products[7], Allegro Microsystems[8] and Toshiba[9], where design considerations are evaluated on commercially available LED modules with the help of Mentor Graphics EDA Tools.

Khkkal et al[10] has studied the complexity of VLSI design systems, which is ever increasing. Quick completion of the design is also demanded which compel the ASIC designers to create their own comprehensive and integrated CAD system from different vendors[10]. Open systems called CAD frameworks are available from different vendors, which make the process of tools integration easy[10]. In this paper ASIC development process is described and issues relating CAD tools are discussed along with the stat-of-the-art CAD framework and its impact on ASIC design is described[10].

VLSI system designs are greatly improved by ASIC technology. It contracts the circuits produced with standard ICs to a single dedicated chip [10 and references therein]. ASIC design time can be made shorter by selecting a comprehensive, integrated and compatible set of ASIC design tools, this will lead to produce cost effective product and reduce the designer’s burden imposed by the data flow of the design through the CAD tools[10]. Thus, the concept of CAD framework is evolved which includes the need to rapidly transfer complex ASIC technology to other engineering disciplines. The CAD framework initiative (CFI), has established guidelines for standard CAD framework[10].

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Details

Seiten
69
Jahr
2011
ISBN (eBook)
9783656497929
ISBN (Buch)
9783656498070
Dateigröße
6.4 MB
Sprache
Deutsch
Katalognummer
v233255
Institution / Hochschule
International Islamic University
Note
Schlagworte
dedicated chip design generation leds

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Titel: Dedicated Chip Design for the Generation of colors through RGB LEDs