Adders are one of the widely used digital components in digital integrated circuit design. Addition is the basic operation used in almost all computational systems. Therefore, the efficient implementation and design of arithmetic units requires the binary adder structures to be implemented in an equally efficient manner. A ripple carry adder has smaller area but less speed. A carry look-ahead adder is faster though its area requirements are high. Carry select adders (CSLA) lie in middle. In this work a novel carry select adder using Binary Excess Converter (BEC) is proposed. It provides good compromise between cost and performance thereby establishing a proper trade-off between time and area complexities. In this work Tanner EDA is used for the comparison of all adders - Ripple carry adder, Bitwise carry select adder, Square root carry select adder, proposed carry select adder using BEC.
Keywords: Carry Select Adder, Binary Excess Converter, Fast Adder.
In recent years, the increasing demand for high-speed arithmetic units in microprocessors, image processing units and DSP chips has paved the path for development of high-speed adders as addition is an indispensable operation in almost every arithmetic unit; also it acts as the basic building block for synthesis of all other arithmetic computations. To increase portability of systems and battery life, area and power are the critical factors of concern. Even in Servers and Personal Computers (PC), power dissipation is an important design parameter. In today’s scenario, design of area-efficient and power- efficient high-speed logic systems is the one of the crucial areas of research in VLSI design. In digital adders, the speed of addition is limited by the time required by the carry to propagate through it. Depending on the area, delay and power consumption requirements, several adder implementations have been proposed. Ripple Carry Adders with the most compact design among all types of adders are slowest in speed. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. By gate level modification of CSLA architecture, we can reduce area and power.
The basic motive of this work is to design and develop an efficient less area and low power adder. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. The proposed design reduces area and power as compared with the regular SQRT CSLA with only a slight increase in the delay.